The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to the structure and formation of super vias in back end of line (BEOL) processing.
Modern integrated circuits are more complex and dense with every technology generation. With continued efforts toward reduction of feature size, use of multiple-patterning and other advanced lithography techniques have been on the rise. Also, the metal deposition process has been evolving to support continuous technology scaling. Generally, integrated circuits (ICs) include semiconductor devices formed as a configuration of circuits on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered conductive networks, which can be formed using schemes, such as, for example, single or dual damascene wiring structures.